The present invention relates to a semiconductor integrated circuit system for transmitting a signal among a plurality of LSI circuits (Large Scale Integrated Circuits) through transmission lines, and more particularly to a semiconductor integrated circuit system having a function of automatically adjusting an output resistance value of an LSI output circuit.
When an output resistance value of an LSI output circuit has a mismatching with an impedance of a transmission line, a reflected wave occurs in a transmitted signal and becomes a noise factor, thereby making it impossible to transmit the signal at a high speed. In order to transmit a signal at a high speed, the output resistance value of the LSI's output circuit has to be matched with the impedance of the transmission line accordingly.
U.S. Pat. No. 4,719,369 (J-P-A-62-38616) and Digest of Technical Papers of International Solid-State Circuits Conference 95 (February, 1995, pp. 40-41) entitled "A CMOS Gate array with 600 Mb/s Simultaneous Bidirectional I/O Circuits" describe technologies in which an output circuit having a plurality of MOS (Metal Oxide Semiconductor) circuits, each having a different gate width (i.e. different internal resistance value), arrayed in parallel to each other is used as an LSI output circuit and an output resistance value is matched with the characteristic impedance of a transmission line by selectively supplying an input to the gates of these MOS transistors, thereby resulting in an impedance matching being effected. The disclosures of U.S. Pat. No. 4,719,369 and the Digest of Technical Papers are hereby incorporated by reference.